The performance of a metal-oxide-semiconductor field effect transistor (MOSFET) is evaluated in terms of its response speed, on-off current ratio, threshold voltage, and the like. To increase the response speed and the on-off current ratio and decrease the threshold voltage of the MOSFET, the MOSFET should have a gate oxide layer with a decreased thickness. However, the thinner the gate oxide layer is, the more easily the gate oxide layer is broken down by charge accumulated at a gate electrode when a gate voltage is relatively high, resulting in failure of the MOSFET.
To increase a breakdown voltage of the MOSFET while maintaining a relatively high response speed, a relatively large on-off current ratio and a relatively low threshold voltage, the charge accumulating at the gate should be eliminated to avoid breakdown of the gate oxide layer.
A conventional MOSFET typically exhibits a large gate-drain capacitance Cgd because a gate oxide layer below a gate has a small thickness. Consequently, a large amount of electric charge may be easily accumulated on the gate electrode of the device to break down the gate oxide layer, and hence the performance of withstanding high voltage of the MOSFET is poor. As an improved prior art, there is provided a MOSFET structure as shown in FIG. 1, in which the MOSFET is formed in an N− epitaxy layer 1 on N+ substrate 2. The bottom of the N+ substrate 2 is covered with a metal stack of Ti/Ni/Ag as a drain metal 8. A trench 3 extends into the N− epitaxy layer 1 from an upper surface of the N− epitaxy layer 1. A lower portion of the inner surface of the trench 3 is covered with a first insulating layer 4, and an upper portion of the inner surface of the trench 3 is covered with a second insulating layer 5, as a gate oxide layer. The first insulating layer 4 has a thickness larger than that of the second insulating layer 5. A polysilicon protection electrode 6 is formed at an upper portion of the inner surface of the trench 3, with a side wall surrounded by the second insulating layer 5 and a bottom contacting the first insulating layer 4. A gate 7 is formed in the trench 3 and surrounded by the polysilicon protection electrode 6. A lower portion of the gate 7 is located below the polysilicon protection electrode 6 and surrounded by the first insulating layer 4. An upper portion of the gate 7 is adjacent to the polysilicon protection electrode 6 and surrounded by the second insulating layer 5. That is, the protection polysilicon electrode 6 is located between the gate 7 and an upper portion of the inner surface of the trench 3. In this structure, the polysilicon protection electrode 6 is added between the gate 7 and the N− epitaxy layer 1 which is used as a drain. The protection electrode is connected to a source, and thus is an actual source of the device.
This structure is proposed for converting a gate-drain capacitance Cgd into a gate-source capacitance Cgs and a drain-source capacitance Cds, so that an effect of the gate-drain capacitance Cgd on the device is reduced and a breakdown voltage of the device is improved. However, the gate 7 and the polysilicon protection electrode 6 should be well insulated in this structure, which means many difficulties in the process. Consequently, the device has variable breakdown voltage and poor reliability, and the manufacture process for the structure includes complex steps, resulting in increased manufacture cost.